Reading a specification is a continuous process that anyone can learn. Stefan guides you through the steps of this process:
AMIQ Blog: How to Read a Specification:
You can draw a picture without lifting the pencil by using constraint random generation:
VerificationGentleman: Fun and Games with CRV: Draw This Without Lifting Your Pencil
Writing assertions might be easy, but qualifying them it’s a different story. SVAUnit is the framework that simplifies and speeds up the qualification process:
AMIQ Blog: How to Verify SystemVerilog Assertions with SVAUnit
To buy or not to buy a VIP? That is the question. Tudor explores a bit the possible answers:
VerificationGentleman: Cooking at Home or Eating Out? – The Pros and Cons of Homegrown VIP
Laxman Sahoo from ArrowDevices presents three scenarios in which the SystemVerilog threads are not OOP safe:
ArrowDevices: OOPs! 3 Issues That Show System Verilog Threads are Not OOP Safe!
In