VerificationAcademy started to collect verification patterns on the Patterns Library webpage.
Mentor Graphics wrote an article introducing this new page.
LearnUVMVerification explains in an intuitive way the UVM reporting. They also provided us with Part 2 of “How virtual sequence works” (this is Part 1 in case you missed it).
Zeev Kirshenbaum/Cadence, presents in one of the Whiteboard Wednesday episode how stimulus can be driven to a DUT via a TLM 2.0 connection without prior knowledge of the protocol used by DUT:
Cadence: Whiteboard Wednesdays – Reusable Data-Driven Verification Using TLM 2.0
Cristian Slav/CFSVision, inspects the capabilities of SystemVerilog’s “interface class” construct and proposes a way of emulating a multiple inheritance behavior:
Multiple Inheritance In SystemVerilog
Tudor Timisescu/VerificationGetleman, presents a way of ending an UVM test in a clean and safe way:
VerificationGentleman: An Overview of UVM End-of-Test Mechanisms
Stefan Birman/AMIQ presents How to Check Out-Of-Order Transactions and plans to upload it as a new pattern on the VerificationAcademy’s Patterns Library webpage.
Either you are a designer or not we advise you to read Jason Yu’s compelling article about Clock Domain Crossing (CDC):
VerilogPro: Clock Domain Crossing Techniques – Part 1
Keisuke Shimizu/ClueLogic, enhances a previously designed driver in order to receive responses:
UVM Tutorial for Candy Lovers – 31. Provides Responses?
Specman Team/Cadence implemented a new extension to the e-language templates:
Cadence: e Templates – Cool Tool, Now Even Cooler
We plan to post the Recommended Articles few days sooner than the end of the month.
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One Response
Great Work Ionel and Team.