Highlights of DVCon US 2017

Hot Topics

The main highlight of the conference by far was the emerging Portable Stimulus Standard (PSS), which was presented through a combination of tutorials, panels and sessions.
Other highlights included discussions around standards, e.g. IEEE1800, IEEE1800.2 and PSS.
SystemVerilog/UVM and High Level Synthesis topics provided more of a backdrop to the conference.

Tutorials

“Tutorial 1: Creating Portable Stimulus Models with the Upcoming Accellera Standard” (Portable Stimulus Working Group, Accellera Systems Initiative)” was very well received. The presenters adopted a pragmatic approach and went deep into technical details and usage scenarios.

“Tutorial 2: Introducing IEEE 1800.2 – The Next Step for UVM” described in detail the first verification methodology to become an IEEE standard. Built on top of UVM 1.2, the new specification also aims to clarify and simplify the LRM.

“Tutorial 4: Reinventing SoC Verification – It Is about Time” (Cadence) introduced the audience to the new multi-core simulator XCelium and the system verification tool PerSpec, which addresses the PSS.

“Tutorial 5: Stuck on a Desert Island without Simulation – Only Formal! How Do I Verify My Rescue Drone’s RTL?” (Mentor Graphics) presented a hypothetical situation in which a drone controller needs to be verified using formal techniques only and showed how this can be achieved using the tools available in the Mentor suite.

Technical Presentations

“7.1 Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation” (Eldon G. Nelson, Intel Corp.) showed how a test can collect more coverage data and exercise more functionality by using simulator checkpoints and SystemVerilog reseeding.

“7.2 Optimizing Random Test Constraints Using Machine Learning Algorithms” (Stan Sokorac, ARM, Inc.) used machine learning, clustering and a new approach to defining code coverage to improve the speed of finding corner cases and bugs inside the RTL.

“7.3 Dynamic Regression Suite Generation Using Coverage-Based Clustering” provided an in-depth analysis of clustering code coverage and how this can be used to optimize the regressions suits.

“2.1 DPI Redux. Functionality. Speed. Optimization” comprised a presentation of Direct Programming Interface (DPI) API and some use cases. It served as an introduction or good refresher on the subject, depending on the experience level of the attendee.

“2.2 Efficient SCE-MI Usage to Accelerate TBA Performance” presented the Standard Co-Emulation Modeling Interface (SCE-MI), which is mostly used for communication between simulation and emulation platforms.

“2.3 New Constrained Random and Metric-Driven Verification Methodology using Python” (Marek Cieplucha, Warsaw University of Technology) presented a way to verify designs using the Python-based Cocotb platform. This was another instance of engineers trying to go around SystemVerilog by using a general-purpose programming language (at DVCon Europe 2014, Puneet Goel presented VLang, a hardware verification library based on D-language).

And last but not least, “11.2 Yet Another Memory Manager (YAMM)” (Andrei Vintila, AMIQ) gave a presentation of the YAMM library and answered questions from UVM contributors.

Harry Foster (Mentor Graphics) also gave a quick overview entitled “Trends in Functional Verification: A 2016 Industry Study” – a good summary of Mentor’s blog post series.

Posters

“4p.14 Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee” (Thomas Ellis, Mentor Graphics) presented a Jenkins regression management plugin. It’s not that often that you see one of the big vendors leveraging the power of Open Source to provide continuous integration support. Jenkins is a very popular continuous integration engine and it has been used before for ASIC/FPGA and embedded projects (see Oleg Nenashev’s presentation here).

“4P.9 Use of Portable Stimulus to Verify Task Dispatching and Scheduling Functions in an LTE Switch” (Adnan Hamid, Breker Verification Systems) described a real-life application of PSS on an LTE switch.

Panels

Adnan Hamid (Breker Verification Systems) moderated the “Users Talk Back on Portable Stimulus” panel. It was an interesting discussion that revealed some users’ concerns and comprehension issues and provided valuable feedback for the Portable Stimulus Working Group, Accellera Systems Initiative.

Jonathan Bromley (Verilab) moderated the “SystemVerilog Jinxed Half My Career: Where Do We Go From Here?” panel. Jonathan’s panel attempted to stir up the hornet’s nest as to the future of SystemVerilog as a hardware verification language. It was an interesting discussion containing a lot of history but the central question remained unanswered.

Best Paper

This year’s Best Paper Award (sponsored by Verilab) went to Stan Sokorac of ARM, Inc. for “Optimizing Random Test Constraints Using Machine Learning Algorithms”.

Expo

DVCon Expo gave us an opportunity to spend quality time with existing and potential AMIQ customers. But AMIQ’s booth was no exception: there were queues of people waiting to talk to all the different vendors.

Acknowledgements

Many thanks to this year’s organizers and Technical Program Committee for the, as always, excellent service and content.
I would like to thank Daniel Ciupitu and Andrei Vintilă for their contributions to this article.

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