We present to you the SystemVerilog and VHDL Grammars in HTML format. The grammars represent the BNF (Backus-Naur Form) notation in an HTML format, with hyperlinks, anchors and tooltips. You can also download them from the GitHub repository.
John Neil, from AgileSOC, continues his reflection on how verification engineers should think about their testbench code: AgileSOC: Balancing Verification Development With Delivery.
Cadence continues its series of SystemVerilog code optimization. They are provided as guidelines, which if thought before writing a single line of code, can help with simulation performance: Part II, Part III.
Here is a new way of controlling e-language generator. It is done by the help of the so called Range Generated Fields: Empowering Generation – Range Generated Fields (RGF).
In June the verification community had an opportunity to share ideas and solutions regarding verification, by means of Verification Futures 2018 conference. If you missed it, you can check out the presentation slides and videos over here: Verification Futures 2018.