Out of this DVCon presentation Tudor got inspired and extended the solution of adding constraints into their own objects. Take a look at his new UVM journey: Favor Composition Over Inheritance – Even for Constraints
Elihai Maicas, from Intel, started a series of verification tips. Here is one of them on how to turn assertions off: Dynamically Turn-off a System-Verilog Assertion
Chris Spear, from Mentor, presents in an intuitive way what are parameterized classes and static properties of the SystemVerilog classes.