After a 4 years pause, Jason Yu, from Intel, wrote a new article on his website Verilog Pro. It is more of a tutorial, about the always block from Verilog/SystemVerilog. I like his writing style and it worth reading. As he puts it in words: ” I have a new goal to create a series of articles to help new engineers transition from “textbook knowledge” to real world knowledge needed to become a digital design engineer“.
Extending a method in e-language is straightforward due to the following constructs: is also, is first, is only. But in certain situations things get a bit unclear. Cristian Slav, posted on his blog an article about how does the return statement work when dealing with method extensions.
A new entry on our list: Michael Green has a blog about verification. My colleagues have spotted this article about the history of constrained random verification and why do we do it in this way. It is a nice introduction for someone who is in the learning stages of verification methodologies.
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