Recommended Articles – July 2022

Elihai Maicas describes how to use SystemVerilog command line to control the value of a SystemVerilog class field and how to enable or disable SystemVerilog constraints. The two LinkedIn posts are a must read for any engineer that wants to add extra-flexibility to the verification environment control. The first post presents how to add hierarchy to an uvm_object class and the second one uses the implementation from the first post in order to turn on/off a constraint-block from the command-line.

Coaching the next generation of [verification] engineers requires to build work relationships based on trust, communication and shared values. Setting internship expectations is the first thing we do for the internship to start off on the right foot.

One of the most important component within a verification environment is the scoreboard. Debugging scoreboards can be very difficult and the worst type of errors are those involving race conditions. Here is a complete and interesting approach on how to avoid race conditions when dealing with data coming from parallel threads. Of course, this is not the only solution/way of dealing with race conditions. But it is the first one which provides so many levels of details, openly in the web.