Hi there! Our colleague Andrei wrote last month a verification article about how to accelerate the debugging process in verification by using error clustering. You can check out the article here: Regression Failure Triage using ECTB Parameter Clustering
I would also like to bring some visibility to this rather old DVCon article: SystemVerilog Constraint Layering via Reusable Randomization Policy Classes. This paper is very insightful showing a way of reusing constraints while also better organizing them.
And since we recently attended the DVCon US 2025, here are some recommendations of papers:
- Don’t Go Changing: How to Code Immutable UVM Objects
- Sequencer Containers – A Unified and Simple Technique to Execute Both Sequences
- Guardians of the Chip: Mastering Next-Gen Security for SoCs and IPs
These papers have not yet been uploaded to the DVCon platform, but I will update the links once they are available. In the meantime you can do your own research on the DVCon platform, and browse through verification articles from all DVCon events.
Enjoy!
In