Ionut shares with us the highlights of DVCon-US 2016 conference. Ionut attended various presentations and also contributed an SVAUnit tutorial.
“A picture is worth a thousand words”. Stefan takes that principle and applies it on DUT data flows representation, so let the picture speak for itself:
How To Graphically Represent DUT’s Data Flows
Munjal continues to address topics from SystemVerilog and UVM. This time he focuses on killing a process in SystemVerilog and using sub-phases and the phase jump concept from UVM.
Keisuke Shimizu shows us how to customize message format in UVM 1.2 and how to use randc to generate all types of a sequence item.
VerificationGentleman explores the implementation of a reflection mechanism in SystemVerilog:
VerificationGentleman: The Humble Beginnings of a SystemVerilog Reflection API
Handling reset when using UVM is an important task for a verification environment. CFSVision suggests one way of doing it:
CFSVision: SystemVerilog: How To Handle Reset In UVM
Efrat Shneydor shows a nice way of building generic scoreboards by using templates. Take a look and feel the full power of e-language constructs:
Cadence: Building Efficient Scoreboards
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Team, Appreciate for such great Wikipedia of Verification