Every design or verification engineer needed at some point in time a basic compile/run script. Go2UVM presents a basic compile/run script that supports all 4 major simulators (Incisive, VCS, QuestaSim and RivieraPro):
Go2UVM: Generic Makefile for UVM simulations
Go2UVM shows the basics of using variable delays in SystemVerilog Assertions:
GO2UVM: Handling variable delays in SystemVerilog Assertions
Manish Singhal opens a new topic: emulation. In this post he introduces the reader to emulation and explains the basic difference between emulation, simulation and prototyping:
LearnUVMVerification: What is Emulation?
Munjal explores a different way of creating stimulus using UVM’s uvm_random_stimulus class:
Munjal: UVM Random Stimulus Generator
Every activity domain makes use of patterns and functional verification is no exception. AMIQ engaged into a quest of discovering and revealing functional verification patterns. Here is the 4’th entry on our list of Functional Verification Patterns:
AMIQ Blog: Functional Coverage Patterns: The Counter
AMIQ is dedicated to introduction of functional verification as a study subject in the Romanian technical colleges. Here is another step forward:
AMIQ Blog: Pre-Silicon Verification Course at Politehnica University of Timișoara
AMIQ was present at the DVCon Europe 2016 in Germany, Munich. Ionuț Ciocîrlan presents the highlights of this year’s conference. Technical curating is not easy, but Ionuț makes it feel simple and pleasant to read:
AMIQ Blog: Highlights of DVCon Europe 2016