UVM provides callbacks mechanism that allows one to expand code’s functionality. Munjal explains advanced usage of callbacks in UVM.
You might remember, from the highlights of DVCon US 2017 conference, that we recommended a paper about constrained random and dynamic seed manipulation (“Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation”). The presenter, Eldon Nelson, working on Intel, owns a blog called Ten Thousand Failures and he made his paper publicly available in his latest June post. Check all the details of his solution over here: IMPROVING CONSTRAINED RANDOM TESTING – SECOND PLACE PAPER AT DVCON 2017.
Mark Glasser from Verification Land, has written an interesting article, Fun with Type Handles, about working with type handles in SystemVerilog. It is more or less a design pattern, used also inside UVM’s code. The pattern helps out when dealing with SystemVerilog types at run-time.
Cristian from CFSVision, started a series about how to handle reset in UVM. He takes his first part of the series and expands it with an explanation of the race conditions in relation to the order of reset threads: SystemVerilog: How To Handle Reset In UVM (part 2).
Horia from AMIQ, continues the series of posts about packing/unpacking in SystemVerilog. This month the focus is placed on the unpacking mechanism from SystemVerilog:How to Unpack Data Using the SystemVerilog Streaming Operators (>>, <<). I consider it to be one of the best tutorials about packing and unpacking.