Jason, from VerilogPro, dives into the details of generate constructs from verilog and how they can be used to build a configurable RTL: Verilog Generate, Configurable RTL Designs
Horia has come with some alternative implementations for bitwise coverage in SystemVerilog. Here you can see his implementations: How To: Alternative ways to implement bitwise coverage
Cadence has shared some nice macro code for its Specman users. The macros are helpful when dealing with coverage (minimum and maximum of a type). Read the full details