After a long pause, Tudor Timisescu wrote a new post about compilation time of SystemVerilog code and how it is impacted by the code aggregation in SystemVerilog packages. Under certain conditions, changing a single file might result in recompilation of the whole code. Find out why in Bigger Is Not Always Better: Builds Are Faster with Smaller Packages
SystemVerilog includes a feature called variable shadowing. Usually, this feature is considered a bit dangerous and care must be taken, but Cristian from CFSVision has found a benefit in using it. Read about Cristian’s findings in SystemVerilog: How To Hide Your Fields So That Anyone Can Find Them
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