Last week I attended the “FPGA Front Runner: FPGA Verification Strategies” conference hosted by Alpinum Consulting.
In this blog post I aim to share an overview of the topics discussed.
The conference began with an insightful look into Rolls-Royce’s journey, from its origins as a luxury car manufacturer in the early 20th century to its evolution into a leader in aerospace and power systems. Dave Sanders from Rolls Royce emphasized the company’s shift away from car manufacturing and highlighted the growing importance of electronics in Rolls-Royce’s current and future innovations. On-site attendees were able to attend an exclusive tour of the Rolls Royce facilities.
VHDL Testbenches using UVVM and OSVVM Frameworks
After the introduction, we delved into VHDL testbenches, focusing on the use of UVVM and OSVVM frameworks with examples based on AXI-stream verification. The first presentation demonstrated how easily VHDL testbenches can be structured for FPGA and ASIC verification, showcasing the simplicity of using UVVM for both basic and advanced testbench designs. Espen Tallaksen from EmLogic emphasized the efficiency gains achieved by employing structured test harnesses, high-level commands, and thorough verification components. In the second presentation, Jim Lewis from SynthWorks Design shifted the focus to the OSVVM framework, highlighting its ability to provide a comprehensive, open-source verification methodology for VHDL. By utilizing entity/architecture constructs and familiar VHDL elements, OSVVM offers a streamlined yet powerful alternative to complex SystemVerilog-based methodologies, making advanced verification accessible to VHDL engineers.
Cocotb – The SystemVerilog contender for Pythonistas
The following sections were focused on the cocotb framework, showcasing its advantages for modern verification. In the first session, Philipp Wagner from FOSSi Foundation introduced cocotb as a Python-based, simulator-agnostic tool that brings a software-like approach to chip verification, highlighting its productivity and ease of use. It also covered the new features in cocotb 2.0, offering tips for updating existing testbenches. The second session, by Christian Tchilikov from Semify GmbH, explored how cocotb efficiently bridges the gap between Python and hardware simulation tools, enabling complex testbenches with minimal engineering overhead. With built-in support for key verification tasks like random input generation and coverage tracking, cocotb allows engineers to easily implement high-level abstractions and verification modules, making it a versatile alternative to traditional SystemVerilog approaches.
Continuous Integration with Atlassian Bamboo and Matlab
The final presentation by Dave Amor from Ultra Maritime focused on the integration of Atlassian Bamboo with MathWorks tools to enhance FPGA development in safety-critical environments. The presentation outlined how Continuous Integration practices and Agile methodologies streamline the development process, enabling consistent and resilient outcomes for mission-critical applications.