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How to Connect SystemVerilog with Octave

When we must verify a highly computational RTL, we may deal with complicated mathematical functions and algorithms. Implementing and debugging an RTL model can be

Andra Socianu, Daniel Ciupitu November 21, 2014 12 Comments

How to print `timescale in Verilog, SystemVerilog and VHDL

Sometimes you need to make sure the correct time unit and precision are applied for each module down the instance tree, especially when there are

Stefan Birman October 31, 2014 4 Comments

How to Stop the Simulation on `uvm_error

The default behavior of `uvm_error is to continue the simulation once the message is reported. Although one can argue over Accelera’s default choice, there are

AMIQ Consulting August 8, 2014 2 Comments

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