Recommended Articles – January 2023

SystemVerilog/UVM code reuse is reaching the next level. Andrei Vintilă and Sergiu Duda have developed a framework/architecture called Externally Controlled Testbench (aka ECTB), initially presented

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Recommended Articles – September 2022

Cristian / CFSVision has enhanced the standard UVM messaging with a new `uvm_infos macro that accepts multiple message tags. `uvm_infos enhances the fine tuning of

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