Recommended Articles – October 2020

AMIQ has released a new UVC that facilitates register accesses. It is called Register Agent: Register Agent: A UVC for Register Access. Manish from Learn

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Recommended Articles – September 2020

Did you know that you can match strings using regular expressions from within SystemVerilog code? UVM implements a function called uvm_re_match. My colleague, Florin Oancea,

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Recommended Articles – August 2020

Ioana Cristea from Amiq shows how to achieve a non blocking communication between the SystemVerilog simulator and an external component, like Python: Non-Blocking Socket Communication

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