SystemVerilog Archives - Page 10 of 27

UVM Register Model to IP-XACT Application

This post presents a simple application for exporting existing UVM/SystemVerilog register models to an IP-XACT file. You can use this application to generate IP-XACT models

AMIQ Consulting January 24, 2017 1 Comment

Functional Coverage Patterns: The Counter

This post explains the functional verification of counters and it is part of a series of posts exploring functional coverage patterns. The first post in

Stefan Birman November 11, 2016 2 Comments

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Recommended Articles – January 2017

UVM Register Model to IP-XACT Application

Functional Coverage Patterns: The Counter