How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<) The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, Read More AMIQ Consulting May 29, 2017 26 Comments
How to Pack Data Using the SystemVerilog Streaming Operators (>>, <<) The verification of digital circuits requires dealing with bits and bytes. It is not a trivial thing to pack or unpack bits, bytes, half words, Read More AMIQ Consulting May 29, 2017 25 Comments
How To Reduce the Number of VIP Instances using Accessor Classes In this post I demonstrate how to use parameterization and accessor classes in order to reduce a variable number of VIP instances to a single Read More Stefan Birman May 9, 2017 No Comments